Amplification circuit

ABSTRACT

An amplifier circuit including a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit including a PMOS transistor ( 11 ), an NMOS transistor ( 12 ), and the like is provided with an NMOS transistor ( 13 ) connected to the NMOS transistor ( 12 ) to increase a source voltage of the NMOS transistor ( 12 ) and DC offset detecting means for detecting a DC offset and applying a voltage adjusted so as to reduce the DC offset to a gate of the NMOS transistor ( 13 ).

TECHNICAL FIELD

[0001] The present invention relates to an amplifier circuit, andparticularly to a CMOS inverter circuit rendered applicable to analogsignal processing by eliminating a DC offset caused by variations inelement characteristics. The variations occur in each manufacturingprocess of an NMOS transistor and a PMOS transistor forming a CMOS.

BACKGROUND ART

[0002] Recently, as production of digital apparatus has increased withprogress of digital signal processing technology, CMOS integratedcircuits have been widely used in semiconductor devices provided withinthe digital apparatus. However, there are cases where it is easier toprocess high-frequency signals, video signals, audio signals, and thelike as analog signals. In addition, to realize A/D converter circuits,D/A converter circuits, clock oscillator circuits, and the like requiresanalog signal processing.

[0003] Bipolar transistors have good suitability as analog signalprocessing circuits. CMOS has been considered to have low suitability asanalog signal processing circuits, except for a part of analog signalprocessing circuits such as sample-and-hold circuits or the like.However, CMOS inverter circuits, though of a very simple configuration,have advantages of a wide input dynamic range, high gain, excellentcurrent supply capability, and the like. It is expected that reductionof overall circuit scale and improvement of performance will be realizedby using a CMOS inverter circuit as an analog signal processing circuit.

[0004]FIGS. 13A and 13B are diagrams showing an example of configurationof a CMOS inverter circuit as an analog signal processing circuit. FIG.13A shows the CMOS inverter circuit itself. FIG. 13B shows a circuitconfiguration in which a virtual voltage source and the like forproviding an ideal operating point in performing analog signalprocessing are added to facilitate description of operatingcharacteristics of the CMOS inverter circuit. In FIGS. 13A and 13B,reference numeral 201 denotes a voltage source; reference numeral 202denotes a PMOS transistor; reference numeral 203 denotes an NMOStransistor; reference numeral 204 denotes a ground part; referencenumeral 205 denotes an input terminal; reference numeral 206 denotes anoutput terminal; reference numeral 207 denotes a load resistancedetermined by drain resistance of the MOS transistors; and referencenumeral 208 denotes a voltage source virtually set for bias voltage. LetVdd be a voltage value of the voltage source 201, Vdd/2 be a voltagevalue of the voltage source 208, Rd be a resistance value of the loadresistance 207, Ip be a drain current of the PMOS transistor 202, In bea drain current of the NMOS transistor 203, Id be a current flowingthrough the load resistance 207, Vg be a voltage value of an inputvoltage at the input terminal 205, and Vo be a voltage value of anoutput voltage at the output terminal 206.

[0005] Operating characteristics of the CMOS inverter circuit shown inFIGS. 13A and 13B will next be described. In the case of using the CMOSinverter circuit as an analog signal processing circuit, for as wide aninput and an output dynamic range as possible, bias setting is desiredto be made such that the output voltage is Vo=Vdd/2 when the inputvoltage is Vg=Vdd/2. The drain current Ip of the PMOS transistor 202 andthe drain current In of the NMOS transistor 203 when such bias settingis made are expressed by an equation (1) and an equation (2),respectively. $\begin{matrix}{{Ip} = {{\frac{Mp}{2}( {{Vdd} - {Vg} - {Vtp}} )^{2}} = {\frac{Mp}{2}( {{Vg} - {Vtp}} )^{2}}}} & (1) \\{{In} = {\frac{Mn}{2}( {{Vg} - {Vtn}} )^{2}}} & (2)\end{matrix}$

[0006] where Mp is a drain current coefficient of the PMOS transistor202; Vtp is a threshold voltage of the PMOS transistor 2022; Mn is adrain current coefficient of the NMOS transistor 203; and Vtn is athreshold voltage of the NMOS transistor 203.

[0007] As shown in FIG. 13B, the output voltage Vo is determined by theresistance value Rd of the load resistance 207 determined by the drainresistance of the MOS transistors and the current Id flowing through theload resistance. The output voltage Vo is given by an equation (3). Torealize proper bias setting, a condition for Vo=Vg=Vdd/2 is given by anequation (4). $\begin{matrix}{{Vo} = {{\frac{Vdd}{2} + {( {{Ip} - {In}} ){Rd}}} = {\frac{Vdd}{2} + {IdRd}}}} & (3) \\{{Id} = {{{Ip} - {In}} = {{{\frac{Mp}{2}( {{Vg} - {Vtp}} )^{2}} - {\frac{Mn}{2}( {{Vg} - {Vtn}} )^{2}}} = 0}}} & (4)\end{matrix}$

[0008] As shown in the equation (4), Vo=Vg when parameters such as thedrain current coefficients Mp and Mn and the threshold voltages Vtp andVtn of the PMOS transistor 202 and the NMOS transistor 203 coincide witheach other. Hence, desired bias setting is realized by equalizing theparameters related to element characteristics of the PMOS transistor 202and the NMOS transistor 203.

[0009] It is known, however, that the parameters related to elementcharacteristics of the PMOS transistor 202 and the NMOS transistor 203generally vary greatly due to a slight difference in a manufacturingenvironment occurring in each manufacturing process (such a variation inthe element characteristics of the MOS transistors occurs in eachmanufacturing process. The variation will be hereinafter referred to asa manufacturing variation). Therefore Vo is not equal to Vg. On thebasis of variations in the element characteristics, Vo>Vg when Ip>In,and Vo<Vg when Ip<In. Hence, even when the input voltage is set toVg=Vdd/2 for bias setting, the output voltage Vo deviates from Vdd/2,causing a so-called DC offset.

[0010] Thus, because of the DC offset occurring according to themanufacturing variation, a sufficient output dynamic range cannot beobtained, and the CMOS inverter circuit as it is not suitable for use asan analog signal processing circuit such as a high-gain amplifier, abuffer amplifier, or the like.

DISCLOSURE OF INVENTION

[0011] The present invention has been made to solve problems asdescribed above, and it is accordingly an object of the presentinvention to provide an amplifier circuit including a CMOS invertercircuit capable of eliminating a DC offset caused by manufacturingvariations and thus applicable to analog signal processing.

[0012] According to the present invention, there is provided anamplifier circuit having a CMOS inverter circuit including a first PMOStransistor, a first NMOS transistor, and the like, in which theamplifier circuit includes both or either one of first voltage shiftmeans for increasing a source voltage of the first NMOS transistor toreduce a DC offset and second voltage shift means for decreasing asource voltage of the first PMOS transistor to reduce the DC offset.

[0013] With such a configuration, it is possible to reduce the DC offsetand increase the dynamic range of the output voltage, so that the CMOSinverter circuit can be used as an analog signal processing circuit.Further, with a configuration including both the first voltage shiftmeans and the second voltage shift means, irrespective of relation inmagnitude between threshold voltages of the PMOS transistor and the NMOStransistor and relation in magnitude between drain current coefficientsof the PMOS transistor and the NMOS transistor, it is possible to reducethe DC offset and increase the dynamic range of the output voltage.

[0014] In the amplifier circuit according to the present invention, thevoltage shift means includes a second MOS transistor interposed betweenthe first NMOS transistor and a ground part or between the first PMOStransistor and a voltage source, and DC offset detecting means forapplying a voltage adjusted so as to reduce the DC offset to a gate ofthe second MOS transistor.

[0015] With such a configuration, the source voltage of the first NMOStransistor can be increased to an appropriate level according to anamount of DC offset detected, or the source voltage of the first PMOStransistor can be decreased to an appropriate level according to theamount of DC offset detected, so that the DC offset can be eliminatedcompletely. Thus, performance of the CMOS inverter circuit as an analogsignal processing circuit can be improved.

[0016] In the amplifier circuit according to the present invention, theDC offset detecting means includes: a third PMOS transistor formedidentically with the first PMOS transistor; a third NMOS transistorformed identically with the first NMOS transistor; a biasing voltagesource; a fourth MOS transistor interposed between the third NMOStransistor and the ground part or between the third PMOS transistor andthe voltage source, and formed identically with the second MOStransistor; and an operational amplifier having an inverting input partconnected to an input part of a CMOS including the third PMOS transistorand the third NMOS transistor and having a non-inverting input partconnected to an output-part of the CMOS, for applying an output voltageto the gate of the second MOS transistor and a gate of the fourth MOStransistor.

[0017] With such a configuration, it is possible to realize the DCoffset detecting circuit with a simple circuit configuration and reducea circuit scale of an analog signal processing circuit or the like usingthe DC offset detecting circuit.

[0018] In the amplifier circuit according to the present invention, theoperational amplifier includes: a fifth NMOS transistor and a sixth NMOStransistor having drains connected to each other to form a differentialpair, the fifth NMOS transistor having a gate connected to thenon-inverting input part and the sixth NMOS transistor having a gateconnected to the inverting input part; a fifth PMOS transistor and asixth PMOS transistor having gates connected to each other to form acurrent mirror; a seventh NMOS transistor having a drain connected to asource of the fifth NMOS transistor; an eighth NMOS transistor having adrain connected to a source of the sixth NMOS transistor; a ninth NMOStransistor having a drain connected to a drain of the fifth PMOStransistor; and a tenth NMOS transistor having a drain connected to adrain of the sixth PMOS transistor; wherein a gate of the seventh NMOStransistor, a gate of the tenth NMOS transistor, and the source of thesixth NMOS transistor are connected to each other; a gate of the eighthNMOS transistor, a gate of the ninth NMOS transistor, and the source ofthe fifth NMOS transistor are connected to each other; and either a partconnecting the drain of the fifth PMOS transistor with the drain of theninth NMOS transistor or a part connecting the drain of the sixth PMOStransistor with the drain of the tenth NMOS transistor is connected toan output part.

[0019] With such a configuration, the differential pair including thefifth NMOS transistor and the sixth NMOS transistor and a negativeconductance circuit including the seventh NMOS transistor and the eighthNMOS transistor form an amplifier having a high mutual conductance.Thus, a high-gain operational amplifier can be obtained withoutincreasing size of the MOS transistors and without increasing biascurrent. Also, a circuit scale of an analog signal processing circuit orthe like using the operational amplifier can be reduced.

[0020] In the amplifier circuit according to the present invention, theoperational amplifier includes: a fifth PMOS transistor and a sixth PMOStransistor having drains connected to each other to form a differentialpair, the fifth PMOS transistor having a gate connected to thenon-inverting input part and the sixth PMOS transistor having a gateconnected to the inverting input part; a fifth NMOS transistor and asixth NMOS transistor having gates connected to each other to form acurrent mirror; a seventh PMOS transistor having a drain connected to asource of the fifth PMOS transistor; an eighth PMOS transistor having adrain connected to a source of the sixth PMOS transistor; a ninth PMOStransistor having a drain connected to a drain of the fifth NMOStransistor; and a tenth PMOS transistor having a drain connected to adrain of the sixth NMOS transistor; wherein a gate of the seventh PMOStransistor, a gate of the tenth PMOS transistor, and the source of thesixth PMOS transistor are connected to each other; a gate of the eighthPMOS transistor, a gate of the ninth PMOS transistor, and the source ofthe fifth PMOS transistor are connected to each other; and either a partconnecting the drain of the fifth NMOS transistor with the drain of theninth PMOS transistor or a part connecting the drain of the sixth NMOStransistor with the drain of the tenth PMOS transistor is connected toan output part.

[0021] With such a configuration, the differential pair including thefifth PMOS transistor and the sixth PMOS transistor and a negativeconductance circuit including the seventh PMOS transistor and the eighthPMOS transistor form an amplifier having a high mutual conductance.Thus, a high-gain operational amplifier can be obtained withoutincreasing size of the MOS transistors and without increasing biascurrent. Also, a circuit scale of an analog signal processing circuit orthe like using the operational amplifier can be reduced.

[0022] According to the present invention, there is provided anamplifier circuit including a CMOS inverter including a first PMOStransistor and a first NMOS transistor connected in series with eachother, voltage control means for variably controlling a source potentialof one MOS transistor of the first PMOS transistor and the first NMOStransistor, and voltage shift means for changing a source potential ofthe other MOS transistor to eliminate a DC offset.

[0023] With such a configuration, by appropriately changing the sourcepotential of the one MOS transistor and operating the voltage shiftmeans so as to eliminate the DC offset, it is consequently possible tocontrol a gain of the amplifier circuit provided as a CMOS including thefirst PMOS transistor and the first NMOS transistor. Thus an amplifiercircuit capable of eliminating a DC offset and controlling the gain canbe obtained.

[0024] In the amplifier circuit according to the present invention, thevoltage control means includes a MOS transistor for voltage controlconnected to a source of the one MOS transistor, and a variable voltagesource connected to a gate of the MOS transistor for voltage control.

[0025] With such a configuration, it is possible to change the sourcepotential of the one MOS transistor by a simple configuration, and thussimplify circuit configuration.

[0026] In the amplifier circuit according to the present invention, thevoltage shift means includes a MOS transistor for voltage shiftingconnected to a source of the other MOS transistor, and DC offsetdetecting means for detecting a DC offset and applying a voltageadjusted so as to eliminate the DC offset to a gate of the MOStransistor for voltage shifting.

[0027] With such a configuration, the source potential of the other MOStransistor can be changed to an appropriate level according to theamount of DC offset detected. Thus, an amplifier circuit that canreliably eliminate a DC offset and has a high precision can be obtained.

[0028] In the amplifier circuit according to the present invention, theDC offset detecting means includes: a comparing circuit obtained byconnecting MOS transistors formed identically with the first PMOStransistor, the first NMOS transistor, the MOS transistor for voltagecontrol, and the MOS transistor for voltage shifting, respectively, inidentical order; and an operational amplifier having an inverting inputpart and a non-inverting input part connected to an input part and anoutput part, respectively, of a CMOS inverter including the PMOStransistor corresponding to the first PMOS transistor and the NMOStransistor corresponding to the first NMOS transistor within thecomparing circuit, and having an output part connected to gates of thetwo MOS transistors for voltage shifting; wherein the variable voltagesource is also connected to a gate of the MOS transistor for voltagecontrol on a side of the comparing circuit.

[0029] With such a configuration, it is possible to realize the DCoffset detecting means for detecting a DC offset with high precision bya simple configuration, and thus simplify circuit configuration.

[0030] The amplifier circuit according to the present invention furtherincludes a first load MOS transistor interposed between a signal outputpart and a voltage source and having a drain and a gate short-circuited,and a second load MOS transistor interposed between the signal outputpart and a ground part and having a drain and a gate short-circuited.

[0031] With such a configuration, a load for extracting a voltage outputcan be provided by using the MOS transistors. It is thus possible toallow integration and reduce circuit scale.

BRIEF DESCRIPTION OF DRAWINGS

[0032]FIG. 1 is a circuit diagram of assistance in explaining operatingprinciples of a DC offset detecting circuit according to the presentinvention;

[0033]FIG. 2 is a circuit diagram showing a DC offset detecting circuitincluded in an amplifier circuit according to a first embodiment of thepresent invention;

[0034]FIG. 3 is a circuit diagram showing a configuration of theamplifier circuit according to the first embodiment of the presentinvention;

[0035]FIG. 4 is a circuit diagram showing an example of configuration ofan operational amplifier used in the amplifier circuit according to thefirst embodiment of the present invention;

[0036]FIG. 5 is a circuit diagram showing another example ofconfiguration of the operational amplifier used in the amplifier circuitaccording to the first embodiment of the present invention;

[0037]FIG. 6 is a circuit diagram showing a configuration of anamplifier circuit according to a second embodiment of the presentinvention;

[0038]FIG. 7 is a circuit diagram showing an example of configuration ofan operational amplifier used in the amplifier circuit according to thesecond embodiment of the present invention;

[0039]FIG. 8 is a circuit diagram showing another example ofconfiguration of the operational amplifier used in the amplifier circuitaccording to the second embodiment of the present invention;

[0040]FIG. 9 is a circuit diagram showing a configuration of anamplifier circuit according to a third embodiment of the presentinvention;

[0041]FIG. 10 is a circuit diagram showing a configuration of anamplifier circuit according to a fourth embodiment of the presentinvention;

[0042]FIG. 11 is a circuit diagram showing a configuration of anamplifier circuit according to a fifth embodiment of the presentinvention;

[0043]FIG. 12 is a circuit diagram showing a configuration of anamplifier circuit according to a sixth embodiment of the presentinvention; and

[0044]FIGS. 13A and 13B are diagrams showing an example of configurationof a CMOS inverter circuit as an analog signal processing circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0045] Embodiments of the present invention will hereinafter bedescribed with reference to the accompanying drawings. Incidentally, inorder to clarify correspondences between elements of the embodimentsthat are described in the embodiments of the present invention andelements or means of the invention that are described in claims, theelements or means of the invention, which are described in the claimsand correspond to the respective elements of the embodiments, will beindicated by parentheses following the respective elements of theembodiments as appropriate in description below of the embodiments ofthe present invention.

[0046] First Embodiment

[0047]FIG. 1 is a diagram of assistance in explaining operatingprinciples of a DC offset detecting circuit according to the presentinvention. In FIG. 1, reference numeral 1 denotes a voltage source;reference numeral 2 denotes a PMOS transistor (third PMOS transistor);reference numeral 3 denotes an NMOS transistor (third NMOS transistor);reference numeral 4 denotes a ground part; reference numeral 5 denotes avoltage source interposed between a source of the NMOS transistor 3 andthe ground part 4, for increasing a source voltage of the NMOStransistor 3 to reduce a DC offset; reference numeral 6 denotes an inputterminal; and reference numeral 7 denotes an output terminal. A backgate of the PMOS transistor 2 is connected to a source of the PMOStransistor 2, and a back gate of the NMOS transistor 3 is connected tothe ground part 4. Let Vdd be a voltage value of the voltage source 1,Ip be a drain current of the PMOS transistor, In be a drain current ofthe NMOS transistor, Id be a current flowing to the output terminal 7,Vs be a voltage value of the voltage source 5 (hereinafter referred toas a shift voltage), Vg be an input voltage, and Vo be an outputvoltage.

[0048] Operating characteristics of a CMOS inverter circuit shown inFIG. 1 will next be described. Also in this case, evaluation regarding aDC offset is performed with Vg=Vdd/2 for appropriate bias setting. Thedrain current Ip of the PMOS transistor 2 and the drain current In ofthe NMOS transistor 3 under the above conditions are given by anequation (5) and an equation (6), respectively. $\begin{matrix}{{Ip} = {{\frac{Mp}{2}( {{Vdd} - {Vg} - {Vtp}} )^{2}} = {\frac{Mp}{2}( {{Vg} - {Vtp}} )^{2}}}} & (5) \\{{In} = {\frac{Mn}{2}( {{Vg} - {Vs} - {Vtn}} )^{2}}} & (6)\end{matrix}$

[0049] Hence, the current Id as a difference between the drain currentIp of the PMOS transistor 2 and the drain current In of the NMOStransistor 3 is given by an equation (7). $\begin{matrix}{{Id} = {{{Ip} - {In}} = {{\frac{Mp}{2}( {{Vg} - {Vtp}} )^{2}} - {\frac{Mn}{2}( {{Vg} - {Vs} - {Vtn}} )^{2}}}}} & (7)\end{matrix}$

[0050] As is clear from the equation (7), it is possible to set Id=0 byappropriately adjusting the voltage value of the shift voltage Vs. Atthis time, the output voltage Vo coincides with the input voltage Vg.The voltage value of the shift voltage Vs that can set Id=0 iscalculated from the following equation (8): $\begin{matrix}{{Vs} = {{Vg} - {Vtn} - {\sqrt{\frac{Mp}{Mn}}( {{Vg} - {Vtp}} )}}} & (8)\end{matrix}$

[0051] When a drain current coefficient Mp of the PMOS transistor 2 anda drain current coefficient Mn of the NMOS transistor 3 are equal toeach other, for example, Vs=Vtp−Vtn, and hence the voltage value of theshift voltage is determined. In operation by a single power source,Vs≧0, and therefore a DC offset of the output voltage can be eliminatedonly when Vtp≧Vtn. Incidentally, when Vtp<Vtn, the DC offset can besimilarly eliminated by interposing a voltage source for voltageshifting between a source of the PMOS transistor 2 and the voltagesource 1.

[0052] When a threshold voltage Vtp of the PMOS transistor 2 and athreshold voltage Vtn of the NMOS transistor 3 are equal to each other,the voltage value of the shift voltage Vs can be determined on the basisof the following equation (9), setting Vtp=Vtn=Vt. $\begin{matrix}{{\therefore{Vs}} = {( {1 - \sqrt{\frac{Mp}{Mn}}} )( {{Vg} - {Vt}} )}} & (9)\end{matrix}$

[0053] In operation by a single power source, Vs≧0 and Vg−Vt>0, andtherefore a DC offset of the output voltage can be eliminated only whenMp≦Mn. Incidentally, when Mp>Mn, the DC offset can be similarlyeliminated by interposing a voltage source for voltage shifting betweenthe source of the PMOS transistor 2 and the voltage source 1.

[0054] Description will next be made of a DC offset detecting circuit(DC offset detecting means) that can automatically adjust the shiftvoltage to eliminate the DC offset caused by manufacturing variations.FIG. 2 is a circuit diagram showing a DC offset detecting circuitaccording to a first embodiment of the present invention. In FIG. 2, thesame reference numerals as in FIG. 1 denote the same or correspondingparts, and therefore description thereof will be omitted. Referencenumeral 8 denotes an NMOS transistor (fourth NMOS transistor) interposedbetween a source of an NMOS transistor 3 and a ground part 4; andreference numeral 9 denotes an operational amplifier (first operationalamplifier) having a non-inverting input part connected to an outputterminal 7, an inverting input part connected to an input terminal 6,and an output part connected to a gate of the NMOS transistor 8. A backgate of the NMOS transistor 8 is connected to the ground part 4.

[0055] Description will next be made of operating characteristics of theDC offset detecting circuit shown in FIG. 2.

[0056] A drain current Ip of a PMOS transistor 2 is given by an equation(10); a drain current In of the NMOS transistor 3 is given by anequation (11); and a drain current In of the NMOS transistor 8 is givenby an equation (12). Analysis will be performed assuming that in orderto simplify description, the NMOS transistor 3 and the NMOS transistor 8are formed identically and that element characteristics such as draincurrent coefficients Mn, threshold voltages Vtn, and the like of theNMOS transistor 3 and the NMOS transistor 8 are equal to each other. Itis to be noted that the DC offset detecting circuit according to thepresent invention does not require that the NMOS transistor 3 and theNMOS transistor 8 be formed identically. Even when these transistors areformed differently, it is of course possible to obtain circuitcharacteristics similar to circuit characteristics to be determined bythe following numerical analysis. $\begin{matrix}{{Ip} = {{\frac{Mp}{2}( {{Vdd} - {Vg} - {Vtp}} )^{2}} = {\frac{Mp}{2}( {{Vg} - {Vtp}} )^{2}}}} & (10) \\{{In} = {\frac{Mn}{2}( {{Vg} - {Vs} - {Vtn}} )^{2}}} & (11) \\{{In} = {\frac{Mn}{2}\{ {{2( {{Vn} - {Vtn}} ){Vs}} - {Vs}^{2}} \}}} & (12)\end{matrix}$

[0057] where Vn is a gate voltage of the NMOS transistor 8. Theoperational amplifier 9 applies the gate voltage Vn, whereby the draincurrent of the NMOS transistor 8 operating in a non-saturation regionand the drain current of the NMOS transistor 3 operating in a saturationregion become equal to each other. From the equation (11) and theequation (12), the gate voltage Vn for generating a desired shiftvoltage Vs is determined as expressed by an equation (13).$\begin{matrix}{{{In} = {{\frac{Mn}{2}( {{Vg} - {Vs} - {Vtn}} )^{2}} = {\frac{Mn}{2}\{ {{2( {{Vn} - {Vtn}} ){Vs}} - {Vs}^{2}} \}}}}{( {{Vg} - {Vs} - {Vtn}} )^{2} = {{{{2( {{Vn} - {Vtn}} ){Vs}} - {Vs}^{2}}\therefore{Vn}} = {{{Vtn} + {\frac{1}{2{Vs}}\{ {{Vs}^{2} + ( {{Vg} - {Vs} - {Vtn}} )^{2}} \}}} = {{Vs} - {Vg} - {2{Vtn}} + \frac{( {{Vg} - {Vtn}} )^{2}}{2{Vs}}}}}}} & (13)\end{matrix}$

[0058] Since the shift voltage Vs is determined on the basis of theequation (8) as a voltage value for eliminating a DC offset of a CMOSinverter, the equation (8) is substituted in the equation (13), wherebythe gate voltage Vn to be supplied to the gate of the NMOS transistor 8to eliminate the DC offset caused by manufacturing variations is givenby an equation (14). $\begin{matrix}{{Vn} = {{{{( {1 - \sqrt{\frac{Mp}{Mn}}} ){Vg}} + {\sqrt{\frac{Mp}{Mn}}{Vtp}} - {Vtn} - {Vg} + {2{Vtn}} + \frac{( {{Vg} - {Vtn}} )^{2}}{2\{ {{( {1 - \sqrt{\frac{Mp}{Mn}}} ){Vg}} + {\sqrt{\frac{Mp}{Mn}}{Vtp}} - {Vtn}} \}}}\therefore{Vn}} = {{Vtn} + {\sqrt{\frac{Mp}{Mn}}{Vtp}} - {\sqrt{\frac{Mp}{Mn}}{Vg}} + \frac{( {{Vg} - {Vtn}} )}{2\{ {1 - {\sqrt{\frac{Mp}{Mn}}\frac{{Vg} - {Vtp}}{{Vg} - {Vtn}}}} \}}}}} & (14)\end{matrix}$

[0059] As described above, the voltage value of the gate voltage Vnrequired to be applied according to variations in elementcharacteristics such as the drain current coefficient Mp, drain currentcoefficient Mn, threshold voltage Vtp, threshold voltage Vtn, and thelike of the PMOS transistor 2, the NMOS transistor 3, and the NMOStransistor 8 is uniquely determined on the basis of the equation (14).

[0060] For example, when the drain current coefficient Mp of the PMOStransistor 2 and the drain current coefficient Mn of the NMOStransistors 3 and 8 are equal to each other, and there is a variationbetween the threshold voltage Vtp of the PMOS transistor 2 and thethreshold voltage Vtn of the NMOS transistors 3 and 8, the gate voltageVn is determined from an equation (15). $\begin{matrix}{{Vn} = {{Vtp} + {Vtn} - {Vg} + \frac{( {{Vg} - {Vtn}} )^{2}}{2( {{Vtp} - {Vtn}} )}}} & (15)\end{matrix}$

[0061] When the threshold voltage Vtp of the PMOS transistor 2 and thethreshold voltage Vtn of the NMOS transistors 3 and 8 are equal to eachother, hence Vtp=Vtn=Vt, and there is a variation between the draincurrent coefficient Mp of the PMOS transistor 2 and the drain currentcoefficient Mn of the NMOS transistors 3 and 8, the gate voltage Vn isdetermined from an equation (16). $\begin{matrix}{{Vn} = {{Vt} + {( {\frac{1}{2( {1 - \sqrt{\frac{Mp}{Mn}}} )} - \sqrt{\frac{Mp}{Mn}}} )( {{Vg} - {Vt}} )}}} & (16)\end{matrix}$

[0062] Operation of the DC offset detecting circuit shown in FIG. 2 willnow be described. When an output voltage Vo becomes greater than aninput voltage Vg, a voltage obtained by amplifying a differentialvoltage between the output voltage Vo and the input voltage Vg isapplied to the gate of the NMOS transistor 8. When the gate voltage ofthe NMOS transistor 8 is increased, a drain resistance of the NMOStransistor is reduced, thereby decreasing the output voltage Vo. Thus,the voltage Vn outputted from the operational amplifier 9 converges atsuch a voltage value as to equalize the output voltage Vo and the inputvoltage Vg with each other.

[0063] Description will next be made of an amplifier circuit accordingto the first embodiment of the present invention using a DC offsetdetecting circuit as shown in FIG. 2. FIG. 3 is a circuit diagramshowing a configuration of the amplifier circuit according to the firstembodiment of the present invention. In FIG. 3, the same referencenumerals as in FIG. 2 denote the same or corresponding parts, andtherefore description thereof will be omitted. Reference numeral 10denotes a voltage source (biasing voltage source) for applying a biasvoltage set so as to enable analog signal processing. Reference numeral11 denotes a PMOS transistor (first PMOS transistor) formed identicallywith a PMOS transistor 2. Reference numeral 12 denotes an NMOStransistor (first NMOS transistor) formed identically with an NMOStransistor 3. Reference numeral 13 denotes an NMOS transistor (secondNMOS transistor) formed identically with an NMOS transistor 8. Referencenumeral 14 denotes an input terminal (signal input part). Referencenumeral 15 denotes an output terminal (signal output part). Let Vin bean input voltage at the input terminal 14, and Vout be an output voltageat the output terminal 15. A back gate of the PMOS transistor 11 isconnected to a source of the PMOS transistor 11; a back gate of the NMOStransistor 12 is connected to a ground part 4; and a back gate of theNMOS transistor 13 is connected to the ground part 4. Incidentally, thebiasing voltage source 10 can be realized by various methods such forexample as dividing a power supply voltage of a voltage source 1 byresistance. Since the amplifier circuit is formed within an identicalchip and therefore goes through identical manufacturing processes, thePMOS transistor 2 and the PMOS transistor 11, the NMOS transistor 3 andthe NMOS transistor 12, and the NMOS transistor 8 and the NMOStransistor 13 can each be considered to have element characteristicssuch as drain current coefficients and threshold voltages equal to eachother. That is, a circuit including the PMOS transistor 2, the NMOStransistor 3, and the NMOS transistor 8 is given as a comparing circuitformed identically with a circuit including the PMOS transistor 11, theNMOS transistor 12, and the NMOS transistor 13. The DC offset detectingcircuit (first DC offset detecting means) including the PMOS transistor2, the NMOS transistor 3, the NMOS transistor 8, an operationalamplifier 9, the biasing voltage source 10, and the like, and the NMOStransistor 13 form first voltage shift means for increasing a sourcevoltage of the NMOS transistor 12 to reduce a DC offset.

[0064] Operation of the amplifier circuit shown in FIG. 3 will next bedescribed. As described above in the operation of the DC offsetdetecting circuit shown in FIG. 2, a voltage Vo at a part connecting adrain of the PMOS transistor 2 with a drain of the NMOS transistor 3becomes equal to a bias voltage Vg given by the biasing voltage source10 for setting a bias. Also, as described above, since the PMOStransistor 2 and the PMOS transistor 11, the NMOS transistor 3 and theNMOS transistor 12, and the NMOS transistor 8 and the NMOS transistor 13can each be considered to have identical element characteristics, theoutput voltage Vout can be Vout=Vg when the input voltage Vin is Vin=Vgby applying an output voltage of the operational amplifier 9 to a gateof the NMOS transistor 13, whereby the DC offset can be eliminated. Thatis, the DC offset detecting circuit detects an amount of DC offsetoccurring inherently in a chip where the amplifier circuit having the DCoffset detecting circuit is created, and applies the voltage Vn indexingthe Amount of DC offset to the gate of the NMOS transistor 13 forvoltage shifting, thereby eliminating the DC offset of a CMOS invertercircuit including the PMOS transistor 11, the NMOS transistor 12, andthe like.

[0065] A configuration of the operational amplifier shown in FIG. 2 andFIG. 3 will next be described. FIG. 4 is a circuit diagram showing anexample of configuration of the operational amplifier. In FIG. 4,reference numeral 21 denotes a voltage source; reference numerals 22,23, 24, and 25 denote a PMOS transistor; reference numerals 26, 27, 28,29, and 30 denote an NMOS transistor; reference numeral 31 denotes avoltage source; reference numeral 32 denotes a ground part; referencenumeral 33 denotes an inverting input part; reference numeral 34 denotesa non-inverting input part; and reference numeral 35 denotes an outputpart.

[0066] Sources of the PMOS transistors 22, 23, 24, and 25 are connectedto the voltage source 21. A gate of the PMOS transistor 22 and a gate ofthe PMOS transistor 23 are connected to each other, and are connected toa drain of the PMOS transistor 23. A gate of the PMOS transistor 24 anda gate of the PMOS transistor 25 are connected to each other, and areconnected to a drain of the PMOS transistor 24. The NMOS transistor 26has a drain connected to the drain of the PMOS transistor 23, and a gateconnected to the inverting input part 33. The NMOS transistor 27 has adrain connected to the drain of the PMOS transistor 24, and a gateconnected to the non-inverting input part 34. A source of the NMOStransistor 26 and a source of the NMOS transistor 27 are connected toeach other, and are connected to a drain of the NMOS transistor 30. Adrain of the NMOS transistor 28 is connected to a drain of the PMOStransistor 22, and a drain of the NMOS transistor 29 is connected to adrain of the PMOS transistor 25. A gate of the NMOS transistor 28 and agate of the NMOS transistor 29 are connected to each other, and areconnected to the drain of the NMOS transistor 28. A gate of the NMOStransistor 30 is connected to the voltage source 31. Sources of the NMOStransistors 28, 29, and 30 are connected to the ground part 32. A partconnecting the drain of the PMOS transistor 25 with the drain of theNMOS transistor 29 is connected to the output part 35. Back gates of thePMOS transistors 22, 23, 24, and 25 are connected to the voltage source21. Back gates of the NMOS transistors 26 and 27 are connected to therespective sources of the NMOS transistors 26 and 27. Back gates of theNMOS transistors 28, 29, and 30 are connected to the ground part 32.

[0067] In the operational amplifier as described above, the PMOStransistor 22 and the PMOS transistor 23, the PMOS transistor 24 and thePMOS transistor 25, and the NMOS transistor 28 and the NMOS transistor29 each form a current mirror. The NMOS transistor 30 and the voltagesource 31 form a constant-current source.

[0068] Operation of the operational amplifier shown in FIG. 4 will nextbe described. The inverting input part 33 of the operational amplifieris connected to an input part of a CMOS forming the DC offset detectingcircuit, and the non-inverting input part 34 of the operationalamplifier is connected to an output part of the CMOS forming the DCoffset detecting circuit. Therefore, let Vg be a voltage applied to theinverting input part 33, Vo be a voltage applied to the non-invertinginput part 34, Ig be a drain current flowing through the NMOS transistor26 according to the gate voltage Vg, and Io be a drain current flowingthrough the NMOS transistor 27 according to the gate voltage Vo.

[0069] The drain current of the NMOS transistor 26, that is, a draincurrent of the PMOS transistor 23 is returned by the current mirrorincluding the PMOS transistor 22 and the PMOS transistor 23 to be equalto a drain current of the PMOS transistor 22. The drain current of thePMOS transistor 22, that is, a drain current of the NMOS transistor 28is returned by the current mirror including the NMOS transistor 28 andthe NMOS transistor 29 to be equal to a drain current of the NMOStransistor 29. Thereby the drain current of the NMOS transistor 29 isIg. The drain current of the NMOS transistor 27, that is, a draincurrent of the PMOS transistor 24 is returned by the current mirrorincluding the PMOS transistor 24 and the PMOS transistor 25 to be equalto a drain current of the PMOS transistor 25. Thereby the drain currentof the PMOS transistor 25 is Io. Thus, a current flowing through theoutput part 35 is Io−Ig.

[0070] The output voltage Vn is increased when the drain current Ioflowing in from the PMOS transistor 25 is increased with respect to thedrain current Ig drawn in by the NMOS transistor 29. Conversely, theoutput voltage Vn is decreased when the drain current Ig drawn in by theNMOS transistor 29 is increased with respect to the drain current Ioflowing in from the PMOS transistor 25. Thus, the operational amplifiershown in FIG. 4 outputs the voltage Vn obtained by amplifying adifferential voltage between the output voltage Vo and the input voltageVg of the DC offset detecting circuit.

[0071] Description will next be made of a modification of theoperational amplifier shown in FIG. 2 and FIG. 3. FIG. 5 is a diagramshowing another example of configuration of the operational amplifier.In FIG. 5, reference numeral 41 denotes a voltage source; referencenumeral 42 denotes a PMOS transistor (fifth PMOS transistor); referencenumeral 43 denotes a PMOS transistor (sixth PMOS transistor); referencenumeral 44 denotes an NMOS transistor (fifth NMOS transistor); referencenumeral 45 denotes an NMOS transistor (sixth NMOS transistor); referencenumeral 46 denotes an NMOS transistor (ninth NMOS transistor); referencenumeral 47 denotes an NMOS transistor (seventh NMOS transistor);reference numeral 48 denotes an NMOS transistor (eighth NMOStransistor); reference numeral 49 denotes an NMOS transistor (tenth NMOStransistor); reference numeral 50 denotes a ground part; referencenumeral 51 denotes a non-inverting input part; reference numeral 52denotes an inverting input part; and reference numeral 53 denotes anoutput part.

[0072] Sources of the PMOS transistors 42 and 43 are connected to thevoltage source 41. A gate of the PMOS transistor 42 and a gate of thePMOS transistor 43 are connected to each other, and are connected to adrain of the PMOS transistor 42. A drain of the NMOS transistor 44 and adrain of the NMOS transistor 45 are connected to each other. A gate ofthe NMOS transistor 44 is connected to the non-inverting input part 51,and a gate of the NMOS transistor 45 is connected to the inverting inputpart 52. The drain of the PMOS transistor 42 and a drain of the NMOStransistor 46 are connected to each other. A drain of the PMOStransistor 43 and a drain of the NMOS transistor 49 are connected toeach other. A source of the NMOS transistor 44, a drain of the NMOStransistor 47, a gate of the NMOS transistor 46, and a gate of the NMOStransistor 48 are connected to each other. A source of the NMOStransistor 45, a drain of the NMOS transistor 48, a gate of the NMOStransistor 47, and a gate of the NMOS transistor 49 are connected toeach other. Sources of the NMOS transistors 46, 47, 48, and 49 areconnected to the ground part 50. A part connecting the drain of the PMOStransistor 43 with the drain of the NMOS transistor 49 is connected tothe output part 53. Back gates of the PMOS transistors 42 and 43 areconnected to the voltage source 41. Back gates of the NMOS transistors44 and 45 are connected to the respective sources of the NMOStransistors 44 and 45. Back gates of the NMOS transistors 46, 47, 48,and 49 are connected to the ground part 50.

[0073] In the operational amplifier as described above, a differentialpair including the NMOS transistor 44 and the NMOS transistor 45 and anegative conductance circuit including the NMOS transistor 47 and theNMOS transistor 48 form an amplifier having a high mutual conductance.The PMOS transistor 42 and the PMOS transistor 43, the NMOS transistor46 and the NMOS transistor 48, and the NMOS transistor 47 and the NMOStransistor 49 each form a current mirror.

[0074] Operation of the operational amplifier shown in FIG. 5 will nextbe described. Also in the operational amplifier, the inverting inputpart 52 of the operational amplifier is connected to the input part ofthe CMOS forming the DC offset detecting circuit, and the non-invertinginput part 51 of the operational amplifier is connected to the outputpart of the CMOS forming the DC offset detecting circuit. Therefore, letVg be a voltage applied to the inverting input part 52, Vo be a voltageapplied to the non-inverting input part 51, Ig be a drain currentflowing through the NMOS transistor 45 according to the gate voltage Vg,and Io be a drain current flowing through the NMOS transistor 44according to the gate voltage Vo.

[0075] The drain current of the NMOS transistor 44, that is, a draincurrent of the NMOS transistor 47 is returned by the current mirrorincluding the NMOS transistor 47 and the NMOS transistor 49 to be equalto a drain current of the NMOS transistor 49. Thereby the drain currentof the NMOS transistor 49 is Io. The drain current of the NMOStransistor 45, that is, a drain current of the NMOS transistor 48 isreturned by the current mirror including the NMOS transistor 46 and theNMOS transistor 48 to be equal to a drain current of the NMOS transistor46. The drain current of the NMOS transistor 46, that is, a draincurrent of the PMOS transistor 42 is returned by the current mirrorincluding the PMOS transistor 42 and the PMOS transistor 43 to be equalto a drain current of the PMOS transistor 43. Thereby the drain currentof the PMOS transistor 43 is Ig. Thus, a current flowing through theoutput part 53 is Ig-Io. The output voltage Vn is increased when thedrain current Io drawn in by the NMOS transistor 49 is decreased withrespect to the drain current Ig flowing in from the PMOS transistor 43.Conversely, the output voltage Vn is decreased when the drain current Iodrawn in by the NMOS transistor 49 is increased with respect to thedrain current Ig flowing in from the PMOS transistor 43. The gate of theNMOS transistor 47 is connected to a part connecting the source of theNMOS transistor 45 with the drain of the NMOS transistor 48, and thegate of the NMOS transistor 48 is connected to a part connecting thesource of the NMOS transistor 44 with the drain of the NMOS transistor47. Thereby, when the voltage Vo becomes higher than the voltage Vg, acurrent amount of the current Ig is increased, and a current amount ofthe current Io is decreased substantially. When the voltage Vg becomeshigher than the voltage Vo, the current amount of the current Io isincreased, and the current amount of the current Ig is decreasedsubstantially. Thus, the operational amplifier having negativeconductance characteristics as described above outputs the voltage Vnobtained by amplifying a differential voltage between the output voltageVo and the input voltage Vg of the DC offset detecting circuit.

[0076] A difference between the operational amplifier shown in FIG. 4and the operational amplifier shown in FIG. 5 will be described. An openloop gain of the operational amplifier as shown in FIG. 4 is generallydetermined on the basis of transistor size of the NMOS transistors 26and 27 forming a differential pair and a bias current flowing throughthe constant-current source. Therefore, when the open loop gain is to beincreased to eliminate a DC offset, there arise needs to increase thesize of the MOS transistors and increase the bias current, thusresulting in disadvantages of a larger circuit scale and increasedcurrent consumption.

[0077] On the other hand, in the operational amplifier as shown in FIG.5, a differential pair including the NMOS transistor 44 and the NMOStransistor 45 and a negative conductance circuit including the NMOStransistor 47 and the NMOS transistor 48 form an amplifier having a highmutual conductance. Thus, a high-gain operational amplifier can beobtained without increasing the size of the MOS transistors and withoutincreasing the bias current.

[0078] As described above, according to the first embodiment, the CMOSinverter circuit is formed with voltage shift means for increasing thesource voltage of the NMOS transistor 12 to reduce a DC offset. It istherefore possible to reduce the DC offset and increase a dynamic rangeof the output voltage, so that the CMOS inverter circuit can be used asan analog signal processing circuit. Further, since a correcting circuitdoes not need to be added to the output part of the CMOS including thePMOS transistor 11 and the NMOS transistor 12, it is possible tosuppress degradation in frequency characteristics due to parasiticcapacitance, degradation in noise performance, and increase in currentconsumption.

[0079] Further, the voltage shift means includes the NMOS transistor 13and the DC offset detecting means for detecting a DC offset and applyinga voltage adjusted so as to reduce the DC offset to the gate of the NMOStransistor 13. The voltage shift means can therefore increase the sourcevoltage of the NMOS transistor 12 to an appropriate level according tothe detected DC offset amount to eliminate the DC offset. Thus,performance of the CMOS inverter circuit as an analog signal processingcircuit can be improved.

[0080] Further, the DC offset detecting circuit includes: the PMOStransistor 2 formed identically with the PMOS transistor 11; the NMOStransistor 3 formed identically with the NMOS transistor 12; the NMOStransistor 8 formed identically with the NMOS transistor 13; theoperational amplifier 9 for amplifying a differential voltage betweenthe bias voltage and the output voltage of the CMOS including the PMOStransistor 2, the NMOS transistor 3, and the like; and the like. It istherefore possible to realize the DC offset detecting circuit with asimple configuration and reduce a circuit scale of the amplifier circuitusing the DC offset detecting circuit.

[0081] Further, the operational amplifier 9 includes: the NMOStransistors 44 and 45 forming a differential pair; the NMOS transistors47 and 48 connected to the NMOS transistors 44 and 45, respectively; thePMOS transistors 42 and 43 forming a current mirror; and the NMOStransistors 46 and 49 connected to the PMOS transistors 42 and 43,respectively. Also, the gate of the NMOS transistor 46, the gate of theNMOS transistor 48, and the source of the NMOS transistor 44 areconnected to each other, and the gate of the NMOS transistor 47, thegate of the NMOS transistor 49, and the source of the NMOS transistor 45are connected to each other. Therefore, the differential pair includingthe NMOS transistor 44 and the NMOS transistor 45 and the negativeconductance circuit including the NMOS transistor 47 and the NMOStransistor 48 form an amplifier having a high mutual conductance. Thus,a high-gain operational amplifier can be obtained without increasing thesize of the MOS transistors forming the operational amplifier andwithout increasing the bias current. Also, circuit scales of the DCoffset detecting circuit using the operational amplifier and theamplifier circuit using the DC offset detecting circuit can be reduced.

[0082] Second Embodiment

[0083]FIG. 6 is a circuit diagram showing a configuration of anamplifier circuit according to a second embodiment of the presentinvention. As described above, when operated by a single power source,the amplifier circuit as shown in FIG. 3 can eliminate a DC offset whenVtp≧Vtn and when Mp≦Mn. On the other hand, the amplifier circuitaccording to the second embodiment of the present invention as shown inFIG. 6 can eliminate a DC offset when Vtp<Vtn and when Mp>Mn. Theamplifier circuit according to the second embodiment is different fromthe amplifier circuit according to the first embodiment in this respect.In FIG. 6, the same reference numerals as in FIG. 3 denote the same orcorresponding parts, and therefore description thereof will be omitted.Reference numeral 61 denotes a PMOS transistor (second PMOS transistor)interposed between a source of a PMOS transistor 11 and a voltage source1, for decreasing a source voltage of the PMOS transistor 11 toeliminate a DC offset. Reference numeral 62 denotes a PMOS transistor(fourth PMOS transistor) formed identically with the PMOS transistor 61and interposed between a source of a PMOS transistor 2 and the voltagesource 1. Reference numeral 63 denotes an operational amplifier (secondoperational amplifier) having an inverting input part connected with agate of the PMOS transistor 2 and a gate of an NMOS transistor 3, anon-inverting input part connected with a drain of the PMOS transistor 2and a drain of the NMOS transistor 3, and an output part connected witha gate of the PMOS transistor 61 and a gate of the PMOS transistor 62. Aback gate of the PMOS transistor 61 is connected to the voltage source1, and a back gate of the PMOS transistor 62 is connected to the voltagesource 1. Incidentally, since the amplifier circuit is formed within anidentical chip and therefore goes through identical manufacturingprocesses, the PMOS transistor 2 and the PMOS transistor 11, the NMOStransistor 3 and an NMOS transistor 12, and the PMOS transistor 62 andthe PMOS transistor 61 can each be considered to have elementcharacteristics such as drain current coefficients and thresholdvoltages equal to each other. A DC offset detecting circuit (second DCoffset detecting means) including the PMOS transistor 2, the NMOStransistor 3, the PMOS transistor 62, the operational amplifier 63, abiasing voltage source 10, and the like, and the PMOS transistor 61 formsecond voltage shift means for decreasing the source voltage of the PMOStransistor 11 to reduce a DC offset.

[0084] Operation of the amplifier circuit shown in FIG. 6 will next bedescribed. The operation of the amplifier circuit shown in FIG. 6 isbasically the same as that of the amplifier circuit shown in FIG. 3.Specifically, when an output voltage Vo of a CMOS including the PMOStransistor 2, the NMOS transistor 3, and the like becomes higher than abias voltage Vg, a voltage resulting from amplifying a differentialvoltage between the output voltage Vo and the bias voltage Vg is appliedto the gate of the PMOS transistor 62. When a gate voltage of the PMOStransistor 62 is increased, a drain resistance of the PMOS transistor isincreased, thereby decreasing the output voltage Vo. Thus, the voltageVp outputted from the operational amplifier 63 converges at such avoltage as to equalize the output voltage Vo and the bias voltage Vgwith each other.

[0085] Since the PMOS transistor 2 and the PMOS transistor 11, the NMOStransistor 3 and the NMOS transistor 12, and the PMOS transistor 62 andthe PMOS transistor 61 can each be considered to be formed identicallyand have identical element characteristics, the output voltage Vout canbe Vout=Vg when the input voltage Vin is Vin Vg by applying the outputvoltage Vp of the operational amplifier 63 to the gate of the PMOStransistor 61, whereby a DC offset can be eliminated. That is, the DCoffset detecting circuit detects an amount of DC offset occurringinherently in a chip where the amplifier circuit having the DC offsetdetecting circuit is created, and applies the voltage Vp indexing theamount of DC offset to the gate of the PMOS transistor 61 for voltageshifting, thereby eliminating the DC offset of a CMOS inverter circuitincluding the PMOS transistor 11, the NMOS transistor 12, and the like.

[0086] A configuration of the operational amplifier shown in FIG. 6 willnext be described. FIG. 7 is a circuit diagram showing an example ofconfiguration of the operational amplifier. In FIG. 7, reference numeral71 denotes a voltage source; reference numeral 72 denotes a PMOStransistor; reference numeral 73 denotes a voltage source; referencenumerals 74, 75, 76, and 77 denote a PMOS transistor; reference numerals78, 79, 80, and 81 denote an NMOS transistor; reference numeral 82denotes a ground part; reference numeral 83 denotes an inverting inputpart; reference numeral 84 denotes a non-inverting input part; andreference numeral 85 denotes an output part.

[0087] Sources of the PMOS transistors 72, 74, and 75 are connected tothe voltage source 71. A gate of the PMOS transistor 72 is connected toa negative electrode side of the voltage source 73. A gate of the PMOStransistor 74 and a gate of the PMOS transistor 75 are connected to eachother, and are connected to a drain of the PMOS transistor 74. A sourceof the PMOS transistor 76 and a source of the PMOS transistor 77 areconnected to each other, and are connected to a drain of the PMOStransistor 72. A gate of the PMOS transistor 76 is connected to theinverting input part 83, and a gate of the PMOS transistor 77 isconnected to the non-inverting input part 84. The drain of the PMOStransistor 74 is connected to a drain of the NMOS transistor 78. A drainof the PMOS transistor 76 is connected to a drain of the NMOS transistor79. A drain of the PMOS transistor 77 is connected to a drain of theNMOS transistor 80. A drain of the PMOS transistor 75 is connected to adrain of the NMOS transistor 81. A gate of the NMOS transistor 78 and agate of the NMOS transistor 79 are connected to each other, and areconnected to the drain of the NMOS transistor 79. A gate of the NMOStransistor 80 and a gate of the NMOS transistor 81 are connected to eachother, and are connected to the drain of the NMOS transistor 80. Asource of the NMOS transistor 78, a source of the NMOS transistor 79, asource of the NMOS transistor 80, and a source of the NMOS transistor 81are connected to the ground part 82. A part connecting the drain of thePMOS transistor 75 with the drain of the NMOS transistor 81 is connectedto the output part 85. Back gates of the PMOS transistors 72, 74, and 75are connected to the voltage source 71. Back gates of the PMOStransistors 76 and 77 are connected to the respective sources of thePMOS transistors 76 and 77. Back gates of the NMOS transistors 78, 79,80, and 81 are connected to the ground part 82.

[0088] In the operational amplifier as described above, the PMOStransistor 74 and the PMOS transistor 75, the NMOS transistor 78 and theNMOS transistor 79, and the NMOS transistor 80 and the NMOS transistor81 each form a current mirror. The PMOS transistor 72 and the voltagesource 73 form a constant-current source. As compared with theoperational amplifier shown in FIG. 4, the operational amplifier shownin FIG. 7 is formed only by interchanging NMOS and PMOS with each other.Basic operation of the operational amplifier shown in FIG. 7 is the sameas that of the operational amplifier shown in FIG. 4, and thereforedescription of the operation will be omitted.

[0089] Description will next be made of a modification of theoperational amplifier shown in FIG. 6. FIG. 8 is a diagram showinganother example of configuration of the operational amplifier. In FIG.8, reference numeral 91 denotes a voltage source; reference numeral 92denotes a PMOS transistor (ninth PMOS transistor); reference numeral 93denotes a PMOS transistor (seventh PMOS transistor); reference numeral94 denotes a PMOS transistor (eighth PMOS transistor); reference numeral95 denotes a PMOS transistor (tenth PMOS transistor); reference numeral96 denotes a PMOS transistor (fifth PMOS transistor); reference numeral97 denotes a PMOS transistor (sixth PMOS transistor); reference numeral98 denotes an NMOS transistor (fifth NMOS transistor); reference numeral99 denotes an NMOS transistor (sixth NMOS transistor); reference numeral100 denotes a ground part; reference numeral 101 denotes a non-invertinginput part; reference numeral 102 denotes an inverting input part; andreference numeral 103 denotes an output part.

[0090] A source of the PMOS transistor 92, a source of the PMOStransistor 93, a source of the PMOS transistor 94, and a source of thePMOS transistor 95 are connected to the voltage source 91. A drain ofthe PMOS transistor 92 is connected to a drain of the NMOS transistor98. A drain of the PMOS transistor 95 is connected to a drain of theNMOS transistor 99. A drain of the PMOS transistor 93 is connected to asource of the PMOS transistor 96. A drain of the PMOS transistor 94 isconnected to a source of the PMOS transistor 97. The drain of the PMOStransistor 93, the source of the PMOS transistor 96, a gate of the PMOStransistor 92, and a gate of the PMOS transistor 94 are connected toeach other. The drain of the PMOS transistor 94, the source of the PMOStransistor 97, a gate of the PMOS transistor 93, and a gate of the PMOStransistor 95 are connected to each other. A gate of the PMOS transistor96 is connected to the non-inverting input part 101. A gate of the PMOStransistor 97 is connected to the inverting input part 102. A drain ofthe PMOS transistor 96 and a drain of the PMOS transistor 97 areconnected to each other, and are connected to the ground part 100. Agate of the NMOS transistor 98 and a gate of the NMOS transistor 99 areconnected to each other, and are connected to a drain of the NMOStransistor 98. A source of the NMOS transistor 98 and a source of theNMOS transistor 99 are connected to the ground part 100. A partconnecting the drain of the PMOS transistor 95 with the drain of theNMOS transistor 99 is connected to the output part 103.

[0091] In the operational amplifier as described above, a differentialpair including the PMOS transistor 96 and the PMOS transistor 97 and anegative conductance circuit including the PMOS transistor 93 and thePMOS transistor 94 form an amplifier having a high mutual conductance.The PMOS transistor 92 and the PMOS transistor 94, the PMOS transistor93 and the PMOS transistor 95, and the NMOS transistor 98 and the NMOStransistor 99 each form a current mirror. As compared with theoperational amplifier shown in FIG. 5, the operational amplifier shownin FIG. 8 is formed only by interchanging NMOS and PMOS with each other.Basic operation of the operational amplifier shown in FIG. 8 is the sameas that of the operational amplifier shown in FIG. 5, and thereforedescription of the operation will be omitted.

[0092] A difference between the operational amplifier shown in FIG. 7and the operational amplifier shown in FIG. 8 will be described. An openloop gain of the operational amplifier as shown in FIG. 7 is generallydetermined on the basis of transistor size of the PMOS transistors 76and 77 forming a differential pair and a bias current flowing throughthe constant-current source. Therefore, when the open loop gain is to beincreased to eliminate a DC offset, there arise needs to increase thesize of the MOS transistors and increase the bias current, thusresulting in disadvantages of a larger circuit scale and increasedcurrent consumption.

[0093] On the other hand, in the operational amplifier as shown in FIG.8, a differential pair including the PMOS transistor 96 and the PMOStransistor 97 and a negative conductance circuit including the PMOStransistor 93 and the PMOS transistor 94 form an amplifier having a highmutual conductance. Thus, a high-gain operational amplifier can beobtained without increasing the size of the MOS transistors and withoutincreasing the bias current.

[0094] As described above, as compared with the amplifier circuitaccording to the first embodiment that has a function of reducing a DCoffset when Vtp≧Vtn and when Mp≦Mn, the second embodiment has similareffects to those of the first embodiment in reducing a DC offset and thelike when Vtp<Vtn and when Mp>Mn.

[0095] Third Embodiment

[0096] An amplifier circuit according to a third embodiment of thepresent invention is different from those of the first embodiment andthe second embodiment in that common parts are provided for the firstvoltage shift means for increasing the source voltage of the NMOStransistor forming the CMOS inverter circuit as shown in FIG. 3 and thesecond voltage shift means for decreasing the source voltage of the PMOStransistor forming the CMOS inverter circuit as shown in FIG. 6, wherebythe two voltage shift means are realized in conjunction with each otherby a simple configuration. FIG. 9 is a circuit diagram showing aconfiguration of the amplifier circuit according to the third embodimentof the present invention. In FIG. 9, the same reference numerals as inFIG. 3 and FIG. 6 denote the same or corresponding parts, and thereforedescription thereof will be omitted.

[0097] Operation of the amplifier circuit shown in FIG. 9 will next bedescribed. When Vtp≧=Vtn and when Mp≦=Mn, an operational amplifier 9functions so that a voltage Vn outputted from the operational amplifier9 to an NMOS transistor 8 converges at such a voltage as to equalize anoutput voltage Vo of a CMOS including a PMOS transistor 2 and an NMOStransistor 3 with a bias voltage Vg. When Vtp<Vtn and when Mp>Mn, anoperational amplifier 63 functions so that a voltage Vp outputted fromthe operational amplifier 63 to a PMOS transistor 62 converges at such avoltage as to equalize the output voltage Vo of the CMOS including thePMOS transistor 2 and the NMOS transistor 3 with the bias voltage Vg.

[0098] The PMOS transistor 62 and a PMOS transistor 61, the PMOStransistor 2 and a PMOS transistor 11, the NMOS transistor 3 and an NMOStransistor 12, and the NMOS transistor 8 and an NMOS transistor 13 caneach be considered to be formed identically and have identical elementcharacteristics. Therefore, by inputting the output voltage Vn of theoperational amplifier 9 to the NMOS transistor 13 and by inputting theoutput voltage Vp of the operational amplifier 63 to the PMOS transistor61, an output voltage Vout can be Vout=Vg when an input voltage Vin isVin=Vg. Thereby a DC offset can be eliminated. That is, first DC offsetdetecting means including the PMOS transistor 2, the NMOS transistors 3and 8, the operational amplifier 9, a bias setting voltage source 10,and the like or second DC offset detecting means including the PMOStransistors 2 and 62, the NMOS transistor 3, the operational amplifier63, the bias setting voltage source 10, and the like detects an amountof DC offset occurring inherently in a chip where the amplifier circuitshown in FIG. 9 is created, and applies the voltage Vn indexing thedetected amount of DC offset to a gate of the NMOS transistor 13 forvoltage shifting or applies the voltage Vp indexing the detected amountof DC offset to a gate of the PMOS transistor 61 for voltage shifting.Thereby the DC offset of a CMOS inverter circuit including the PMOStransistor 11, the NMOS transistor 12, and the like can be eliminated.

[0099] As described above, the third embodiment has similar effects tothose of the first embodiment and the second embodiment. Also, the CMOSinverter circuit is provided with both the first voltage shift means forincreasing the source voltage of the NMOS transistor 12 to reduce the DCoffset and the second voltage shift means for decreasing the sourcevoltage of the PMOS transistor 11 to reduce the DC offset. Therefore,irrespective of relation in magnitude between the threshold voltages Vtpand Vtn and relation in magnitude between the drain current coefficientsMp and Mn, it is possible to reduce the DC offset and increase a dynamicrange of the output voltage, so that the amplifier circuit including theCMOS inverter circuit can be used as an analog signal processingcircuit.

[0100] Fourth Embodiment

[0101] An amplifier circuit according to a fourth embodiment of thepresent invention is different from the amplifier circuits according tothe first to third embodiments in that the amplifier circuit accordingto the fourth embodiment has a gain varying function in addition to a DCoffset eliminating function. FIG. 10 is a circuit diagram showing aconfiguration of the amplifier circuit according to the fourthembodiment of the present invention. In FIG. 10, the same referencenumerals as in FIG. 3 denote the same or corresponding parts, andtherefore description thereof will be omitted. Reference numeral 111denotes a PMOS transistor (second PMOS transistor) interposed between asource of a PMOS transistor 11 and a voltage source 1. Reference numeral112 denotes a PMOS transistor (fourth PMOS transistor) formedidentically with the PMOS transistor 111 and interposed between a sourceof a PMOS transistor 2 and the voltage source 1. Reference numeral 113denotes a variable voltage source connected to a gate of the PMOStransistor 111 and a gate of the PMOS transistor 112. Reference numeral114 denotes an NMOS transistor having a function of preventing alatch-up phenomenon occurring at a time of turning on power or the like.

[0102] As described above, since the amplifier circuit shown in FIG. 10is formed within an identical chip and therefore goes through identicalmanufacturing processes, the PMOS transistor 111 and the PMOS transistor112 can be considered to have element characteristics such as draincurrent coefficients and threshold voltages equal to each other.

[0103] In this case, the PMOS transistor 111, the voltage source 113,and the like include voltage control means for variably controlling asource potential of the PMOS transistor 11. A circuit including the PMOStransistor 112, the PMOS transistor 2, an NMOS transistor 3, and an NMOStransistor 8 is given as a comparing circuit formed identically with acircuit including the PMOS transistor 111, the PMOS transistor 11, anNMOS transistor 12, and an NMOS transistor 13.

[0104] The PMOS transistor 112, the PMOS transistor 2, the NMOStransistor 3, the NMOS transistor 8, an operational amplifier 9, abiasing voltage source 10, and the like include DC offset detectingmeans for detecting a DC offset occurring in a CMOS inverter circuitincluding the PMOS transistor 11 and the NMOS transistor 12 in a statein which the source potential of the PMOS transistor 11 is changed bythe voltage control means, and applying a voltage adjusted so as toeliminate the DC offset to a gate of the NMOS transistor 13. Further,the DC offset detecting means and the NMOS transistor 13 include voltageshift means for increasing a source potential of the NMOS transistor 12to eliminate the DC offset.

[0105] Operation of the amplifier circuit shown in FIG. 10 will next bedescribed. Let Vdd be a power supply voltage, Vc be a control voltagesupplied by the variable voltage source 113, Vsp be the source potentialof the PMOS transistor 11 and the PMOS transistor 2, Vg be a biasvoltage supplied by the biasing voltage source 10, and Vn be an outputvoltage of the operational amplifier 9. As already described, thecircuit including the PMOS transistor 112, the PMOS transistor 2, theNMOS transistor 3, and the NMOS transistor 8 is given as a comparingcircuit formed identically with the circuit including the PMOStransistor 111, the PMOS transistor 11, the NMOS transistor 12, and theNMOS transistor 13. The same control voltage Vc is applied to the gateof the PMOS transistor 111 and the gate of the PMOS transistor 112, andthe same voltage Vn for eliminating a DC offset is applied to gates ofthe NMOS transistor 13 and the NMOS transistor 8. Thus, for the biasvoltage Vg, the MOS transistors in corresponding relation perform thesame respective operations. In description below of circuit operation,numerical analysis will be performed assuming that in order tofacilitate understanding, element characteristics of the PMOS transistor111 and the PMOS transistor 11 are equal to each other and elementcharacteristics of the NMOS transistor 12 and the NMOS transistor 13 areequal to each other. It is to be noted that the amplifier circuitaccording to the present invention does not require that the PMOStransistor 111 and the PMOS transistor 11, and the NMOS transistor 12and the NMOS transistor 13 be each formed identically. Even when thesetransistors are formed differently, it is of course possible to obtaincircuit characteristics similar to circuit characteristics to bedetermined by the following numerical analysis.

[0106] An equation (17) is obtained on the basis of a fact that a draincurrent of the PMOS transistor 111 in a non-saturation region and adrain current of the PMOS transistor 11 in a saturation region are equalto each other. An equation (18) is obtained by rearranging the equation(17). Then, by solving the equation (18) for Vsp, Vsp is given asexpressed by an equation (19). As indicated by the equation (19), thesource potential Vsp of the PMOS transistor 11 and the PMOS transistor 2can be controlled by appropriately changing the voltage Vc of thevariable voltage source 113. $\begin{matrix}{{{2( {{Vdd} - {Vc} - {Vtp}} )( {{Vdd} - {Vsp}} )} - ( {{Vdd} - {Vsp}} )^{2}} = ( {{Vsp} - {Vdd} + {Vdd} - {Vg} - {Vtp}} )^{2}} & (17) \\{{{2( {{Vdd} - {Vsp}} )} - {2( {{2{Vdd}} - {Vg} - {Vc} - {2{Vtp}}} )( {{Vdd} - {Vsp}} )} + ( {{Vdd} - {Vg} - {Vtp}} )^{2}} = 0} & (18) \\\begin{matrix}{{Vsp} = {\frac{{Vg} + {Vc}}{2} + {Vtp} -}} \\{{\frac{1}{2}\sqrt{( {{2{Vdd}} - {Vg} - {Vc} - {2{Vtp}}} )^{2} - {2( {{Vdd} - {Vg} - {Vtp}} )^{2}}}}} \\{= {\frac{{Vg} + {Vc}}{2} + {Vtp} -}} \\{{\frac{1}{2}\sqrt{\begin{matrix}( {{Vc}^{2} - {2( {{2{Vdd}} - {Vg} - {2{Vtp}}} ){Vc}} +}  \\{( {{2{Vdd}} - {Vg} - {2{Vtp}}} )^{2} - {2( {{Vdd} - {Vg} - {Vtp}} )^{2}}}\end{matrix}}}} \\{= {\frac{{Vg} + {Vc}}{2} + {Vtp} -}} \\{{\frac{1}{2}\sqrt{{Vc}^{2} - {( {{2{Vdd}} - {Vg} - {2{Vtp}}} ){Vc}} + {2( {{Vdd} - {Vtp}} )^{2}} - {Vg}^{2}}}}\end{matrix} & (19)\end{matrix}$

[0107] The DC offset detecting means applies the voltage Vn to the gateof the NMOS transistor 13 to thereby eliminate a DC offset of the CMOSinverter circuit including the PMOS transistor 111, the PMOS transistor11, the NMOS transistor 12, the NMOS transistor 13, and the like. Anoutput current Io of the CMOS inverter circuit is determined asexpressed by an equation (20). A gain Ga of the CMOS inverter circuit isgiven as expressed by an equation (21). As is clear from the equation(21), the gain Ga of the CMOS inverter circuit can be controlled byappropriately changing the control voltage Vc. $\begin{matrix}{{Io} = {{- {{Mp}( {1 + \sqrt{\frac{Mn}{Mp}}} )}}( {{Vsp} - {Vg} - {Vtp}} ){Vin}}} & (20) \\\begin{matrix}{{Ga} = {\frac{Vout}{Vin} - {{{Mp}( {1 + \sqrt{\frac{Mn}{Mp}}} )}( {{Vsp} - {Vg} - {Vtp}} ){Ro}}}} \\{= {{{Mp}( {1 + \sqrt{\frac{Mn}{Mp}}} )}\{ {\frac{{Vc} - {Vg}}{2} -} }} \\{ {\frac{1}{2}\sqrt{{Vc}^{2} - {2( {{Vdd} - {Vg} - {2{Vtp}}} ){Vc}} + {2( {{Vdd} - {Vtp}} )^{2}} - {Vg}^{2}}} \} {Ro}}\end{matrix} & (21)\end{matrix}$

[0108] where Ro is a resistance value of a load resistance connected toan output terminal 15. Incidentally, the NMOS transistor 114 is off insteady-state operation with a drain-to-source voltage being zero. TheNMOS transistor 114 therefore has no effect on the DC offset correctingoperation.

[0109] As described above, the fourth embodiment includes the voltagecontrol means for variably controlling the source potential of the PMOStransistor 11 and the voltage shift means for increasing the sourcepotential of the NMOS transistor 12 to eliminate a DC offset. Byappropriately changing the source potential of the PMOS transistor 11and operating the voltage shift means so as to eliminate a DC offset, itis consequently possible to control the gain of the CMOS invertercircuit. Thus an amplifier circuit capable of eliminating a DC offsetand controlling the gain can be obtained. In addition, since acorrecting circuit does not need to be added to the output part of theCMOS inverter circuit including the PMOS transistor 11, the NMOStransistor 12, and the like, it is possible to suppress degradation infrequency characteristics due to parasitic capacitance, degradation innoise performance, and increase in current consumption.

[0110] Further, the voltage control means includes the PMOS transistor111 interposed between the source of the PMOS transistor 11 and thevoltage source 1, and the voltage source 113 connected to the gate ofthe PMOS transistor 111. It is therefore possible to change the sourcepotential of the PMOS transistor 11 by a simple configuration, and thussimplify circuit configuration.

[0111] Further, the voltage shift means includes the NMOS transistor 13interposed between a source of the NMOS transistor 12 and a ground part4, and the DC offset detecting means for detecting a DC offset andapplying a voltage adjusted so as to eliminate the DC offset to the gateof the NMOS transistor 13. Therefore, the source potential of the NMOStransistor 12 can be raised to an appropriate level according to anamount of DC offset detected. Thus an amplifier circuit that canreliably eliminate a DC offset and has a high precision can be obtained.

[0112] Further, the DC offset detecting means includes: the PMOStransistor 112 having a gate connected to the variable voltage source113 and formed identically with the PMOS transistor 111; the PMOStransistor 2 connected to the PMOS transistor 112 and formed identicallywith the PMOS transistor 11; the NMOS transistor 3 connected to the PMOStransistor 2 and formed identically with the NMOS transistor 12; theNMOS transistor 8 connected to the NMOS transistor 3 and formedidentically with the NMOS transistor 13; the voltage source 10 forapplying a direct-current bias voltage to a gate of the PMOS transistor2 and a gate of the NMOS transistor 3; and the operational amplifier 9having an inverting input part and a non-inverting input part connectedto an input part and an output part, respectively, of a CMOS includingthe PMOS transistor 2 and the NMOS transistor 3, and having an outputpart connected to the gate of the NMOS transistor 13 and the gate of theNMOS transistor 8. It is therefore possible to realize the DC offsetdetecting means for detecting a DC offset with high precision by asimple configuration, and thus simplify circuit configuration.

[0113] Fifth Embodiment

[0114] An amplifier circuit according to a fifth embodiment of thepresent invention is characterized in that the amplifier circuitaccording to the fifth embodiment has a gain varying function inaddition to a DC offset eliminating function as in the fourthembodiment. FIG. 11 is a circuit diagram showing a configuration of theamplifier circuit according to the fifth embodiment of the presentinvention. In FIG. 11, the same reference numerals as in FIG. 6 and FIG.10 denote the same or corresponding parts, and therefore descriptionthereof will be omitted. Reference numeral 121 denotes an NMOStransistor (second NMOS transistor) interposed between a source of anNMOS transistor 12 and a ground part 4. Reference numeral 122 denotes anNMOS transistor (fourth NMOS transistor) formed identically with theNMOS transistor 121 and interposed between a source of an NMOStransistor 3 and the ground part 4. Reference numeral 123 denotes avariable voltage source connected to a gate of the NMOS transistor 121and a gate of the NMOS transistor 122.

[0115] Since the amplifier circuit described above is formed within anidentical chip and therefore goes through identical manufacturingprocesses, a PMOS transistor 61 and a PMOS transistor 62, a PMOStransistor 11 and a PMOS transistor 2, the NMOS transistor 12 and theNMOS transistor 3, and the NMOS transistor 121 and the NMOS transistor122 can each be considered to have element characteristics such as draincurrent coefficients and threshold voltages equal to each other. Thatis, a circuit including the PMOS transistor 62, the PMOS transistor 2,the NMOS transistor 3, and the NMOS transistor 122 is given as acomparing circuit formed identically with a circuit including the PMOStransistor 61, the PMOS transistor 11, the NMOS transistor 12, and theNMOS transistor 121.

[0116] In the amplifier circuit shown in FIG. 11, the NMOS transistor121, the variable voltage source 123, and the like include voltagecontrol means for variably controlling a source potential of the NMOStransistor 12. The PMOS transistor 62, the PMOS transistor 2, the NMOStransistor 3, the NMOS transistor 122, an operational amplifier 63, abiasing voltage source 10, and the like include DC offset detectingmeans for detecting a DC offset occurring in a CMOS inverter circuitincluding the PMOS transistor 11 and the NMOS transistor 12 in a statein which the source potential of the NMOS transistor 12 is changed bythe voltage control means, and applying a voltage adjusted so as toeliminate the DC offset to a gate of the PMOS transistor 61. Further,the DC offset detecting means and the PMOS transistor 61 include voltageshift means for decreasing a source potential of the PMOS transistor 11to eliminate the DC offset.

[0117] Operation of the amplifier circuit shown in FIG. 11 will next bedescribed. Let Vdd be a power supply voltage, Vc be a control voltagesupplied by the variable voltage source 123, Vsn be the source potentialof the NMOS transistor 12 and the NMOS transistor 3, Vg be a biasvoltage supplied by the biasing voltage source 10, and Vp be an outputvoltage of the operational amplifier 63. As already described, thecircuit including the PMOS transistor 62, the PMOS transistor 2, theNMOS transistor 3, and the NMOS transistor 122 is given as a comparingcircuit formed identically with the circuit including the PMOStransistor 61, the PMOS transistor 11, the NMOS transistor 12, and theNMOS transistor 121. The same control voltage Vc is applied to the gateof the NMOS transistor 121 and the gate of the NMOS transistor 122, andthe same voltage Vp for eliminating a DC offset is applied to gates ofthe PMOS transistor 61 and the PMOS transistor 62. Thus, for the biasvoltage Vg, the MOS transistors in corresponding relation perform thesame respective operations. In description below of circuit operation,numerical analysis will be performed assuming that in order tofacilitate understanding, element characteristics of the PMOS transistor61 and the PMOS transistor 11 are equal to each other and elementcharacteristics of the NMOS transistor 12 and the NMOS transistor 121are equal to each other. It is to be noted that the amplifier circuitaccording to the present invention does not require that the PMOStransistor 61 and the PMOS transistor 11, and the NMOS transistor 12 andthe NMOS transistor 121 be each formed identically. Even when thesetransistors are formed differently, it is of course possible to obtaincircuit characteristics similar to circuit characteristics to bedetermined by the following numerical analysis.

[0118] An equation (22) is obtained on the basis of a fact that a draincurrent of the NMOS transistor 121 in a non-saturation region and adrain current of the NMOS transistor 12 in a saturation region are equalto each other. An equation (23) is obtained by rearranging the equation(22). Then, by solving the equation (23) for Vsn, Vsn is given asexpressed by an equation (24). As is clear from the equation (24), thesource potential Vsn of the NMOS transistor 12 and the NMOS transistor 3can be controlled by appropriately changing the voltage Vc of thevariable voltage source 123. $\begin{matrix}{{{2( {{Vc} - {Vtn}} ){Vsn}} - {Vsn}^{2}} = ( {{Vg} - {Vsn} - {Vtn}} )^{2}} & (22) \\{{{2{Vsn}} - {2( {{Vg} + {Vc} - {2{Vtn}}} ){Vsn}} + ( {{Vg} - {Vtn}} )^{2}} = 0} & (23) \\\begin{matrix}{{Vsn} = {\frac{{Vg} + {Vc}}{2} - {Vtn} -}} \\{{\frac{1}{2}\sqrt{( {{Vg} + {Vc} - {2{Vtn}}} )^{2} - {2( {{Vg} - {Vtn}} )^{2}}}}} \\{= {\frac{{Vg} + {Vc}}{2} - {Vtn} -}} \\{{\frac{1}{2}\sqrt{{Vc}^{2} + {( {{2{Vg}} - {2{Vtn}}} ){Vc}} + ( {{Vg} - {2{Vtn}}} )^{2} - {2( {{Vg} - {Vtn}} )^{2}}}}} \\{= {\frac{{Vg} + {Vc}}{2} - {Vtn} - {\frac{1}{2}\sqrt{{Vc}^{2} + {( {{2{Vg}} - {2{Vtn}}} ){Vc}} - {Vg}^{2} + {2{Vtn}^{2}}}}}}\end{matrix} & (24)\end{matrix}$

[0119] An output current Io and a gain Ga of the amplifier circuit shownin FIG. 11 can be determined as expressed by an equation (25) and anequation (26). As is clear from the equation (26), the gain Ga of theCMOS inverter circuit can be controlled by appropriately changing thecontrol voltage Vc. $\begin{matrix}{{Io} = {{- {{Mn}( {1 + \sqrt{\frac{Mp}{Mn}}} )}}( {{Vg} - {Vsn} - {Vtn}} ){Vin}}} & (25) \\\begin{matrix}{{Ga} = {\frac{Vout}{Vin} = {{- {{Mn}( {1 + \sqrt{\frac{Mp}{Mn}}} )}}( {{Vg} - {Vsn} - {Vtn}} ){Ro}}}} \\{= {{- {{Mn}( {1 + \sqrt{\frac{Mp}{Mn}}} )}}\{ {\frac{{Vg} - {Vc}}{2} -} }} \\{ {\frac{1}{2}\sqrt{{Vc}^{2} + {( {{2{Vg}} - {2{Vtn}}} ){Vc}} - {Vg}^{2} + {2{Vtn}^{2}}}} \} {Ro}}\end{matrix} & (26)\end{matrix}$

[0120] As described above, the fifth embodiment includes the voltagecontrol means for variably controlling the source potential of the NMOStransistor 12 and the voltage shift means for decreasing the sourcepotential of the PMOS transistor 11 to eliminate a DC offset. Byappropriately changing the source potential of the NMOS transistor 12and operating the voltage shift means so as to eliminate a DC offset, itis consequently possible to control the gain of the CMOS invertercircuit. Thus an amplifier circuit capable of eliminating a DC offsetand controlling the gain can be obtained. In addition, since acorrecting circuit does not need to be added to the output part of theCMOS inverter circuit including the PMOS transistor 11 and the NMOStransistor 12, it is possible to suppress degradation in frequencycharacteristics due to parasitic capacitance, degradation in noiseperformance, and increase in current consumption.

[0121] Further, the voltage control means includes the NMOS transistor121 interposed between the source of the NMOS transistor 12 and theground part 4, and the voltage source 123 connected to the gate of theNMOS transistor 121. It is therefore possible to change the sourcepotential of the NMOS transistor 12 by a simple configuration, and thussimplify circuit configuration.

[0122] Further, the voltage shift means includes the PMOS transistor 61interposed between a source of the PMOS transistor 11 and a voltagesource 1, and the DC offset detecting means for detecting a DC offsetand applying a voltage adjusted so as to eliminate the DC offset to thegate of the PMOS transistor 61. Therefore, the source potential of thePMOS transistor 11 can be lowered to an appropriate level according toan amount of DC offset detected. Thus an amplifier circuit that canreliably eliminate a DC offset and has a high precision can be obtained.

[0123] Further, the DC offset detecting means includes: the PMOStransistor 62 formed identically with the PMOS transistor 61; the PMOStransistor 2 connected to the PMOS transistor 62 and formed identicallywith the PMOS transistor 11; the NMOS transistor 3 connected to the PMOStransistor 2 and formed identically with the NMOS transistor 12; theNMOS transistor 122 connected to the NMOS transistor 3, having a gateconnected to the variable voltage source 123, and formed identicallywith the NMOS transistor 121; the voltage source 10 for applying adirect-current bias voltage to a gate of the PMOS transistor 2 and agate of the NMOS transistor 3; and the operational amplifier 63 havingan inverting input part and a non-inverting input part connected to aninput part and an output part, respectively, of a CMOS including thePMOS transistor 2 and the NMOS transistor 3, and having an output partconnected to the gate of the PMOS transistor 61 and the gate of the PMOStransistor 62. It is therefore possible to realize the DC offsetdetecting means for detecting a DC offset with high precision by asimple configuration, and thus simplify circuit configuration.

[0124] Sixth Embodiment

[0125] An amplifier circuit according to a sixth embodiment of thepresent invention is characterized in that MOS transistors are connectedas a load to an output terminal. FIG. 12 is a circuit diagram showing aconfiguration of the amplifier circuit according to the sixth embodimentof the present invention. In FIG. 12, the same reference numerals as inFIG. 11 denote the same or corresponding parts, and thereforedescription thereof will be omitted. Reference numeral 131 denotes anNMOS transistor (first load MOS transistor) interposed between a voltagesource 1 and an output terminal 15, and having a drain and a gateshort-circuited. Reference numeral 132 denotes an NMOS transistor(second load MOS transistor) interposed between a ground part 4 and theoutput terminal 15, and having a drain and a gate short-circuited.Incidentally, the DC offset detecting means and the like shown in FIG.11 are omitted.

[0126] Operation of the amplifier circuit shown in FIG. 12 will next bedescribed. Letting Mn′ be a drain current coefficient of the NMOStransistors 131 and 132, and Gmn′ be a mutual conductance of the NMOStransistors 131 and 132, a resistance value Rd of the load formed by theNMOS transistors 131 and 132 is given as expressed by an equation (27).A gain Gb of the amplifier circuit shown in FIG. 12 is given asexpressed by an equation (28) on the basis of the equation (25) and theequation (27). As is clear from the equation (28), the gain of theamplifier circuit can be set on the basis of a ratio between a draincurrent coefficient Mn of an NMOS transistor 12 and an NMOS transistor121 and the drain current coefficient Mn′ of the NMOS transistor 131 andthe NMOS transistor 132. That is, the gain Gb can be set appropriatelyby changing a ratio of channel length or channel width of the NMOStransistors 131 and 132 to channel length or channel width of the NMOStransistors 12 and 121. $\begin{matrix}{{Rd} = {\frac{1}{{Gmn}^{\prime}} = \frac{1}{2{{Mn}^{\prime}( {{Vg} - {Vtn}} )}}}} & (27) \\{{Gb} = {\frac{{Io} \cdot {Rd}}{Vin} = {{- \frac{Mn}{1{Mn}^{\prime}}}( {1 + \sqrt{\frac{Mp}{Mn}}} )\frac{{Vg} - {Vsn} - {Vtn}}{{Vg} - {Vtn}}}}} & (28)\end{matrix}$

[0127] As described above, the sixth embodiment includes the NMOStransistor 131 interposed between the output terminal 15 and the voltagesource 1, and having a drain and a gate short-circuited, and the NMOStransistor 132 interposed between the output terminal 15 and the groundpart 4, and having a drain and a gate short-circuited. Therefore, a loadfor extracting a voltage output can be provided by using the MOStransistors. It is thus possible to allow integration and reduce circuitscale. Further, the gain of the amplifier circuit can be set on thebasis of a ratio in size such as channel length or channel width betweenthe MOS transistors. Therefore, as compared with a case of extracting avoltage output using a resistance, errors occurring in gain due tomanufacturing variations can be reduced, thus increasing precision ofthe amplifier circuit. It is to be noted that PMOS transistors may beused as load transistors, providing similar effects to those of the NMOStransistors.

[0128] It is to be noted that the amplifier circuits described by way ofthe foregoing first to sixth embodiments do not limit the presentinvention but are disclosed to be illustrative of the present invention.The technical scope of the present invention is defined by claims, andvarious design changes may be made within the technical scope of theinvention described in the claims. For example, a number of CMOSinverter circuits connected to the DC offset detecting circuit as shownin FIG. 3, FIG. 6, FIG. 9, FIG. 10, FIG. 11, and FIG. 12 is not limitedto one; a plurality of CMOS inverter circuits may be connected to the DCoffset detecting circuit. By commonly connecting signal input parts andsignal output parts of the CMOS inverter circuits in such aconfiguration, an amplifier circuit with a high driving capability canbe obtained. Also, while in the sixth embodiment, the load MOStransistors are connected to the output terminal 15 of the amplifiercircuit shown in FIG. 11, it is of course possible to connect load MOStransistors to the output terminal 15 of the amplifier circuit shown inFIG. 3, FIG. 6, FIG. 9, and FIG. 10.

1. An amplifier circuit including a first PMOS transistor; a first NMOStransistor having a drain connected to a drain of said first PMOStransistor; a signal input part connected to a gate of said first PMOStransistor and a gate of said first NMOS transistor; and a signal outputpart connected to a part connecting the drain of said first PMOStransistor with the drain of said first NMOS transistor, wherein saidamplifier circuit includes both or either one of first voltage shiftmeans for increasing a source voltage of said first NMOS transistor toreduce a DC offset and second voltage shift means for decreasing asource voltage of said first PMOS transistor to reduce the DC offset. 2.The amplifier circuit as claimed in claim 1, characterized in that: saidfirst voltage shift means includes: a second NMOS transistor interposedbetween a source of said first NMOS transistor and a ground part; andfirst DC offset detecting means for detecting the DC offset and applyinga voltage adjusted so as to reduce the DC offset to a gate of saidsecond NMOS transistor.
 3. The amplifier circuit as claimed in claim 1,characterized in that: said second voltage shift means includes: asecond PMOS transistor interposed between a source of said first PMOStransistor and a voltage source; and second DC offset detecting meansfor detecting the DC offset and applying a voltage adjusted so as toreduce the DC offset to a gate of said second PMOS transistor.
 4. Theamplifier circuit as claimed in claim 2, characterized in that: saidfirst DC offset detecting means includes: a third PMOS transistor formedidentically with said first PMOS transistor; a third NMOS transistorhaving a drain connected to a drain of said third PMOS transistor andformed identically with said first NMOS transistor; a biasing voltagesource for supplying a direct-current bias voltage to a gate of saidthird PMOS transistor and a gate of said third NMOS transistor; a fourthNMOS transistor having a drain connected to a source of said third NMOStransistor, and formed identically with said second NMOS transistor; anda first operational amplifier having a non-inverting input partconnected to a part connecting the drain of said third PMOS transistorwith the drain of said third NMOS transistor, an inverting input partconnected to a part connecting the gate of said third PMOS transistorwith the gate of said third NMOS transistor, and an output partconnected to the gate of said second NMOS transistor and a gate of saidfourth NMOS transistor.
 5. The amplifier circuit as claimed in claim 3,characterized in that: said second DC offset detecting means includes: athird PMOS transistor formed identically with said first PMOStransistor; a third NMOS transistor having a drain connected to a drainof said third PMOS transistor and formed identically with said firstNMOS transistor; a biasing voltage source for supplying a direct-currentbias voltage to a gate of said third PMOS transistor and a gate of saidthird NMOS transistor; a fourth PMOS transistor having a drain connectedto a source of said third PMOS transistor, and formed identically withsaid second PMOS transistor; and a second operational amplifier having anon-inverting input part connected to a part connecting the drain ofsaid third PMOS transistor with the drain of said third NMOS transistor,an inverting input part connected to a part connecting the gate of saidthird PMOS transistor with the gate of said third NMOS transistor, andan output part connected to the gate of said second PMOS transistor anda gate of said fourth PMOS transistor.
 6. The amplifier circuit asclaimed in claim 4, characterized in that: said first operationalamplifier includes: a fifth NMOS transistor and a sixth NMOS transistorhaving drains connected to each other to form a differential pair, saidfifth NMOS transistor having a gate connected to the non-inverting inputpart and said sixth NMOS transistor having a gate connected to theinverting input part; a fifth PMOS transistor and a sixth PMOStransistor having gates connected to each other to form a currentmirror; a seventh NMOS transistor having a drain connected to a sourceof said fifth NMOS transistor; an eighth NMOS transistor having a drainconnected to a source of said sixth NMOS transistor; a ninth NMOStransistor having a drain connected to a drain of said fifth PMOStransistor; and a tenth NMOS transistor having a drain connected to adrain of said sixth PMOS transistor; wherein a gate of said seventh NMOStransistor, a gate of said tenth NMOS transistor, and the source of saidsixth NMOS transistor are connected to each other; a gate of said eighthNMOS transistor, a gate of said ninth NMOS transistor, and the source ofsaid fifth NMOS transistor are connected to each other; and either apart connecting the drain of said fifth PMOS transistor with the drainof said ninth NMOS transistor or a part connecting the drain of saidsixth PMOS transistor with the drain of said tenth NMOS transistor isconnected to the output part.
 7. The amplifier circuit as claimed inclaim 5, characterized in that: said second operational amplifierincludes: a fifth PMOS transistor and a sixth PMOS transistor havingdrains connected to each other to form a differential pair, said fifthPMOS transistor having a gate connected to the non-inverting input partand said sixth PMOS transistor having a gate connected to the invertinginput part; a fifth NMOS transistor and a sixth NMOS transistor havinggates connected to each other to form a current mirror; a seventh PMOStransistor having a drain connected to a source of said fifth PMOStransistor; an eighth PMOS transistor having a drain connected to asource of said sixth PMOS transistor; a ninth PMOS transistor having adrain connected to a drain of said fifth NMOS transistor; and a tenthPMOS transistor having a drain connected to a drain of said sixth NMOStransistor; wherein a gate of said seventh PMOS transistor, a gate ofsaid tenth PMOS transistor, and the source of said sixth PMOS transistorare connected to each other; a gate of said eighth PMOS transistor, agate of said ninth PMOS transistor, and the source of said fifth PMOStransistor are connected to each other; and either a part connecting thedrain of said fifth NMOS transistor with the drain of said ninth PMOStransistor or a part connecting the drain of said sixth NMOS transistorwith the drain of said tenth PMOS transistor is connected to the outputpart.
 8. An amplifier circuit including a first PMOS transistor; a firstNMOS transistor having a drain connected to a drain of said first PMOStransistor; a signal input part connected to a gate of said first PMOStransistor and a gate of said first NMOS transistor; and a signal outputpart connected to a part connecting the drain of said first PMOStransistor with the drain of said first NMOS transistor, said amplifiercircuit characterized by comprising: voltage control means for variablycontrolling a source potential of said first PMOS transistor; andvoltage shift means for increasing a source potential of said first NMOStransistor to eliminate a DC offset.
 9. The amplifier circuit as claimedin claim 8, characterized in that: said voltage control means includes:a second PMOS transistor interposed between a source of said first PMOStransistor and a voltage source; and a variable voltage source connectedto a gate of said second PMOS transistor.
 10. The amplifier circuit asclaimed in claim 8, characterized in that: said voltage shift meansincludes: a second NMOS transistor interposed between a source of saidfirst NMOS transistor and a ground part; and DC offset detecting meansfor detecting the DC offset and applying a voltage adjusted so as toeliminate the DC offset to a gate of said second NMOS transistor. 11.The amplifier circuit as claimed in claim 10, characterized in that:said voltage control means includes: a second PMOS transistor interposedbetween a source of said first PMOS transistor and a voltage source; anda variable voltage source connected to a gate of said second PMOStransistor; and said DC offset detecting means includes: a third PMOStransistor formed identically with said first PMOS transistor; a thirdNMOS transistor having a drain connected to a drain of said third PMOStransistor and formed identically with said first NMOS transistor; abiasing voltage source for supplying a direct-current bias voltage to agate of said third PMOS transistor and a gate of said third NMOStransistor; a fourth PMOS transistor interposed between a source of saidthird PMOS transistor and the voltage source, having a gate connected tosaid variable voltage source, and formed identically with said secondPMOS transistor; a fourth NMOS transistor interposed between a source ofsaid third NMOS transistor and the ground part, and formed identicallywith said second NMOS transistor; and an operational amplifier having anon-inverting input part connected to a part connecting the drain ofsaid third PMOS transistor with the drain of said third NMOS transistor,an inverting input part connected to a part connecting the gate of saidthird PMOS transistor with the gate of said third NMOS transistor, andan output part connected to the gate of said second NMOS transistor anda gate of said fourth NMOS transistor.
 12. The amplifier circuit asclaimed in claim 8, characterized by further comprising: a first loadMOS transistor interposed between the signal output part and a voltagesource, and having a drain and a gate short-circuited; and a second loadMOS transistor interposed between the signal output part and a groundpart, and having a drain and a gate short-circuited.
 13. An amplifiercircuit including a first PMOS transistor; a first NMOS transistorhaving a drain connected to a drain of said first PMOS transistor; asignal input part connected to a gate of said first PMOS transistor anda gate of said first NMOS transistor; and a signal output part connectedto a part connecting the drain of said first PMOS transistor with thedrain of said first NMOS transistor, said amplifier circuitcharacterized by comprising: voltage control means for variablycontrolling a source potential of said first NMOS transistor; andvoltage shift means for decreasing a source potential of said first PMOStransistor to eliminate a DC offset.
 14. The amplifier circuit asclaimed in claim 13, characterized in that: said voltage control meansincludes: a second NMOS transistor interposed between a source of saidfirst NMOS transistor and a ground part; and a variable voltage sourceconnected to a gate of said second NMOS transistor.
 15. The amplifiercircuit as claimed in claim 13, characterized in that: said voltageshift means includes: a second PMOS transistor interposed between asource of said first PMOS transistor and a voltage source; and DC offsetdetecting means for detecting the DC offset and applying a voltageadjusted so as to eliminate the DC offset to a gate of said second PMOStransistor.
 16. The amplifier circuit as claimed in claim 15,characterized in that: said voltage control means includes: a secondNMOS transistor interposed between a source of said first NMOStransistor and a ground part; and a variable voltage source connected toa gate of said second NMOS transistor; and said DC offset detectingmeans includes: a third PMOS transistor formed identically with saidfirst PMOS transistor; a third NMOS transistor having a drain connectedto a drain of said third PMOS transistor and formed identically withsaid first NMOS transistor; a biasing voltage source for supplying adirect-current bias voltage to a gate of said third PMOS transistor anda gate of said third NMOS transistor; a fourth NMOS transistorinterposed between a source of said third NMOS transistor and the groundpart, having a gate connected to said variable voltage source, andformed identically with said second NMOS transistor; a fourth PMOStransistor interposed between a source of said third PMOS transistor andthe voltage source, and formed identically with said second PMOStransistor; and an operational amplifier having a non-inverting inputpart connected to a part connecting the drain of said third PMOStransistor with the drain of said third NMOS transistor, an invertinginput part connected to a part connecting the gate of said third PMOStransistor with the gate of said third NMOS transistor, and an outputpart connected to the gate of said second PMOS transistor and a gate ofsaid fourth PMOS transistor.
 17. The amplifier circuit as claimed inclaim 13, characterized by further comprising: a first load MOStransistor interposed between the signal output part and a voltagesource, and having a drain and a gate short-circuited; and a second loadMOS transistor interposed between the signal output part and a groundpart, and having a drain and a gate short-circuited.